Integrated circuitry is typically fabricated on and within semiconductor substrates, such a bulk monocrystalline silicon wafers. In the context of this document, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Electrical components fabricated on substrates, and particularly bulk semiconductor wafers, are isolated from adjacent devices by insulating materials, such as insulating oxides. One isolation technique comprises trench isolation, whereby trenches are cut into a substrate and are subsequently filled with insulating oxide. Typical prior art problems associated with such isolation is described with reference to FIGS. 1-3.
Referring first to FIG. 1, a semiconductor wafer fragment 10 is comprised of a bulk monocrystalline silicon wafer having light background p-type doping of, for example, an average concentration of 1.times.10.sup.13 ions/cm.sup.3. A pad oxide layer 14 has been formed over wafer 12, and an oxidation masking layer 16 (typically Si.sub.3 N.sub.4) is formed thereover. Layers 16 and 14 have been patterned as shown whereby the illustrated masking blocks overlie desired active area regions of the semiconductor wafer, and the exposed areas proximate thereto will constitute isolation regions to be formed.
Referring to FIG. 2, wafer fragment 10 is subject to a conventional dry etch chemistry, with or without plasma, which is principally fluorine-based, utilizing example components of one or more of CHF.sub.3, CF.sub.4 and C.sub.2 HF.sub.5. Such chemistry is selective to etch semiconductor wafer material 12 uniformly selective relative to masking layers 16 and 14, and as well has a highly desired degree of anisotropy to produce the illustrated trenches 18 having substantially straight sidewalls 20. Unfortunately, such etching also undesirably produces very sharp corners 22 at the lowestmost corners within trench 18.
Referring to FIG. 3, wafer 10 has been subjected to suitable wet oxidation conditions to form oxide isolation regions 24, with layers 16 and 14 having been subsequently removed. Unfortunately, the sharp corners 22 formed by the above or other etchings undesirably create high electric fields in these locations, and produce other adverse loading effects in the finished circuitry which is detrimental to circuit operation. Accordingly, it would be desirable to provide methods which enable production of trench recessed isolation material which do not require sharp corners.